Clock disabling provides an effective method of dynamic power saving in an electronic device. The technique may, however, cause sudden changes in the electrical current drawn by the electronic device, which may, in turn, cause variations of the supply voltage applied across the electronic device. It can be necessary or advantageous to maintain a supply voltage level that fluctuates as little as possible.
U.S. Pat. Nos. 7,882,458 and 7,900,172 describe methods of analyzing power consumption of a simulated electronic device in a design phase before manufacture.